• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The external electrode in the semiconductor device includes a wiring pad 12, first and second barrier metal layers 161 and 162, a solder wet film 17 and a solder ball 12 from the bottom of the wafer. The first barrier metal layer 161 has a tensile stress and a grain crystal structure, while the second barrier metal layer 162 has a compressive internal stress and a columnar crystal structure. The two-layer structure of the barrier metal layer 16 has an excellent barrier function against Sn diffusion from the solder balls 20 and reduces the internal stress of the barrier metal layer 16.
    公开号:KR20030007227A
    申请号:KR1020020041951
    申请日:2002-07-18
    公开日:2003-01-23
    发明作者:미까기가오루；후루야아끼라；하따노게이스께
    申请人:닛뽕덴끼 가부시끼가이샤；
    IPC主号:
    专利说明:

    Semiconductor device having an external electrode {SEMICONDUCTOR DEVICE HAVING AN EXTERNAL ELECTRODE}
    [46] The present invention relates to a semiconductor device having an external electrode, and more particularly to a semiconductor device having an external electrode including a barrier metal electrode.
    [47] In a semiconductor element, an external electrode is usually formed by mounting a solder ball on a wiring pad connected to an internal wiring of the semiconductor element. The solder balls are bonded to correspond to the electrodes of the wiring board such as the printed circuit board. The semiconductor element is connected to an external circuit by an external electrode including a solder ball or the like, and is mechanically fixed to the wiring board.
    [48] Usually, a barrier metal electrode (electrode layer) is interposed in the semiconductor element so that the tin (Sn) component in the solder ball is prevented from diffusing into the metal layer of the wiring pad of the semiconductor element between the solder ball and the lower layer wiring pad. Usually, Sn is a main component of the solder ball. Since the barrier metal electrode is susceptible to external stress applied through the solder ball, it is desirable to have sufficient mechanical strength while having sufficient barrier function against diffusion of Sn.
    [49] 1 shows a cross section of a structure of a conventional external electrode with solder balls. In the silicon substrate 10, a plurality of interlayer insulating films and a plurality of connecting layers are formed (not shown), so that the wiring pads 12 formed of Al on the top insulating film 11 deposited by plasma-enhanced CVD (PECVD) technology. ) Is formed. The lower film 13 formed of TiN / Ti is interposed between the wiring pad 13 and the interlayer insulating film to improve the adhesive force between the wiring pad 12 and the insulating film 11 and at the same time improve the reliability of the connecting portion. The insulating film 14 covering the wiring pad 12 is provided to have a two-layer structure of a plasma SiO 2 layer and a plasma SiON layer, and has a through hole exposing an upper portion of the wiring pad 12.
    [50] On the wiring pad 12, a TiN / Ti film 13 is applied to improve wiring reliability, and a barrier metal electrode is formed on the TiN / Ti film 13. The barrier metal electrode includes a Ti adhesion film 15, a nickel-vanadium (Ni-V) alloy film 16A serving as a barrier metal layer, and a solder-wet Cu layer 17 with improved wettability of solder. These films are deposited on the entire surface by the sputtering method, and then patterned so as to remain around the through-holes and through-holes formed in the wiring pad 12.
    [51] The polyimide layer 18 is formed in this whole surface, and it patterned so that it may have the opening part 19 for exposing a barrier metal electrode. The solder ball 20 is mounted on the barrier metal electrode to close the opening 19. The barrier metal layer 16A is formed sufficiently thick so as to have a sufficient barrier function to prevent Sn diffusion. The outer surface of the barrier metal electrode is provided with a TiW adhesion layer 21 which improves adhesion with the polyimide layer 18.
    [52] 2 illustrates another conventional prior art of the structure of an external electrode with solder balls. The other external electrode is similar to the conventional external electrode of FIG. 1 except that the wiring pad is formed of an Al—Cu alloy on the conventional external electrode. More specifically, the barrier metal electrode includes a Ti film 51 as a first conductive film, a sputtered Ni film 52 as a second conductive film, a strike-plating Ni film 53 as a third conductive film, It has four film | membrane structures provided with the normal Ni plating film | membrane as a 4th conductive film.
    [53] The Ti film 51 and the sputtered Ni-V alloy film 52 are formed in the through hole and the interlayer insulating film 14 around it. A strike Ni film 53 is formed on the sputtered Ni-V alloy film 52 above the photoresist film 37 and in the openings, and a Ni plating film 54 having a thicker thickness is formed thereon. The solder ball 20 is formed in the solder wettable Cu layer formed in the Ni plating film 54 by the plating method. In order to ensure the adhesion between the strike Ni film 53 and the sputtered Ni alloy film 52, the plating technique of the strike Ni film 53 uses a large plating current instantaneously compared to a strike current, for example, a conventional plating current. By the technique, the strike Ni film 53 having a thickness of 0.1 to 0.3 mu m is formed.
    [54] The external electrode structure of FIG. 1 is an example for forming a single barrier metal layer 16A formed of Ni alloy which prevents Sn diffusion. The barrier metal layer 16A usually has a granular crystal structure, and since the crystals are arranged in a complex manner, the grain boundaries become curvilinear, and the grain boundary diffusion path through which diffusion matches the grain boundaries is long, The barrier performance against the diffusion of Sn becomes high.
    [55] FIG. 3 shows the relationship between the wafer warp after sputtering of the barrier metal layer and the crystal structure of the barrier metal layer depending on the bias voltage upon sputtering of the barrier metal layer. According to Fig. 3, the Ni alloy film having the granular crystal structure has a larger tensile strain. The higher tensile stress causes a problem in the formation of the barrier metal layer having a thick thickness, causing cracks or peel-off of the insulating film 14 under the barrier metal layer in the wiring pad 12. In order to reduce the film stress, the Ni alloy film constituting the barrier metal layer may have a pillar crystal structure instead of the granular crystal structure. However, since the columnar crystal structure reduces the length of the Sn diffusion path due to the straight crystal boundary, the barrier function for preventing Sn diffusion is deteriorated, which is undesirable.
    [56] In another conventional technique of Fig. 2, Ni-plated films 53 and 54 having a thick thickness are obtained in a three-layer structure including electrode films 52 added to Ni-plated films 53 and 54, respectively, Ni films 53 and 54 are plated on 52. The electrode film 52 formed by sputtering is normally exposed to the atmosphere, and a passive Ni oxide film is formed on the electrode film 52. The passive Ni oxide film is chemically stable and difficult to remove, lowers the compressive force of the Ni films 53 and 54, and reduces the bonding strength of the interface between the plating film 53 and the electrode film 52. In the conventional art, since a high temperature eutectic solder material having a relatively small mechanical strength is used for the solder ball 20, such a reduction in the interface bonding strength is that of the solder ball 20 in the conventional art. In terms of mechanical strength, this is not a critical problem.
    [57] On the other hand, the use of lead-free (Pb-free) solder materials for the solder balls 20 is increasing, and lead-free material solder is a material having excellent ductility and high mechanical strength because of its high Sn content. The mechanical strength of the external electrode in another conventional technique is to be determined by the bonding strength of the interface between the Ni plating film 53 and the electrode Ni film 52 formed by sputtering. Further, the development of the small area of the solder bumps reduces the bonding strength per solder bump, and in other conventional techniques, the bonding strength is increased due to the appearance of the electrode Ni film 52 of the passive Ni oxide film formed on the electrode Ni film 52. Emphasize the problem of diminishing.
    [58] As described above, an object of the present invention is to provide a semiconductor device having a barrier metal electrode or an external electrode including a barrier metal layer, which has an excellent barrier function against Sn diffusion into wiring pads, and which damages adjacent structures. In order to prevent that, the internal stress is reduced.
    [1] 1 is a cross-sectional view of an external electrode in a conventional semiconductor device.
    [2] 2 is a cross-sectional view of an external electrode in another conventional semiconductor element.
    [3] 3 is a graph showing the relationship between wafer warpage and RF bias voltage that determines the crystal structure of a sputtered film.
    [4] 4 is a cross-sectional view of an external electrode in the semiconductor device according to the first embodiment of the present invention.
    [5] 5A and 5B are schematic cross-sectional views of a Ni-V alloy film at the external electrode shown in FIG.
    [6] 6 is a graph showing the relationship between the deposition rate of a Ni—V alloy film and the DC sputtering voltage.
    [7] Fig. 7 is a graph showing the relationship between the film stress and the RF bias voltage in the sputtered Ni-V alloy film with the DC sputtering voltage fixedly held, and the relationship between the wafer warpage and the RF bias voltage.
    [8] Fig. 8 is a graph showing the relationship between the film stress and the RF bias voltage in the sputtered Ni-V alloy film with the sputtering voltage fixedly held, and the relationship between the wafer warpage and the RF bias voltage.
    [9] Fig. 9 is a graph showing the relationship between film stress and Ar flow rate in a sputtered Ni-V alloy film with a fixed DC sputtering voltage fixed thereto.
    [10] 10 is a graph showing the relationship between film stress and DC sputtering voltage in a sputtered Ni-V alloy film.
    [11] FIG. 11 is a graph showing wafer warpage at an assembly step of an external electrode while varying the sputtering voltage, film thickness, and bias voltage. FIG.
    [12] 12 is a table showing a relationship between wafer warpage and process conditions in a three-layer structure of a barrier metal layer.
    [13] 13A-13D are cross-sectional views of successive assembly steps of the external electrode of FIG.
    [14] 14 is a cross-sectional view of an external electrode according to a second embodiment of the present invention.
    [15] 15 is a cross-sectional view of the assembly process of the external electrode of FIG. 14.
    [16] 16 is a cross-sectional view of an external electrode according to a third embodiment of the present invention.
    [17] 17 is a cross-sectional view of the assembly process of the external electrode of FIG.
    [18] 18 is a sectional view of an external electrode according to a first modification of the third embodiment of the present invention;
    [19] Fig. 19 is a sectional view of an external electrode according to a second modification of the third embodiment of the present invention.
    [20] 20 is a sectional view of an external electrode according to a third modification of the third embodiment of the present invention;
    [21] ＊ Description of symbols for main parts of the drawings ＊
    [22] 10: silicon substrate
    [23] 11: interlayer insulation film
    [24] 12: wiring pad
    [25] 13: TiN / Ti film
    [26] 14: insulating film
    [27] 15, 41, 51: Ti adhesion film
    [28] 16, 42, 52: Ni-V barrier metal layer
    [29] 161: first barrier metal layer
    [30] 162: second barrier metal layer
    [31] 17, 43: solder Cu layer
    [32] 18: polyimide layer
    [33] 19, 38, 39: opening
    [34] 20: solder ball
    [35] 21, 44: TiW adhesion layer
    [36] 22: beer hall
    [37] 31: first conductive film (Ti adhesion film)
    [38] 32: second conductive film (Ni-V barrier film)
    [39] 33: third conductive film (seed Cu layer)
    [40] 34: Ni plating layer
    [41] 35: solder wet Cu layer
    [42] 36, 40: TiW adhesion film
    [43] 37: photoresist film
    [44] 53: Strike Ni Film
    [45] 54: Ni plating film
    [59] According to a first aspect, the present invention provides a semiconductor device having an external electrode including a wiring pad, a barrier metal electrode, and a solder ball continuously formed on one wafer. The barrier metal electrode includes a plurality of barrier metal layers having a common element and having different internal stresses and / or different crystal structures.
    [60] According to the semiconductor device according to the first aspect of the present invention, the above-mentioned external electrode allows the barrier metal electrode to have a relatively low internal stress and a relatively thick film, so that the barrier metal electrode has excellent barrier function without damaging the adjacent structure. Has
    [61] The term "barrier metal electrode" as used herein refers to an electrode structure comprising a single or a plurality of conductive films and interposed between the solder balls and the lower wiring pads, where the conductive layers and layers are responsible for the diffusion of Sn from the solder balls. At least one barrier metal layer having a barrier function. The barrier metal layer is preferably formed of Ni or Ni alloy.
    [62] In addition, in a second aspect, there is also provided a semiconductor device provided with an external electrode comprising a wiring pad, a barrier metal electrode and a solder ball continuously formed on one wafer. The barrier metal electrode includes at least five conductive layers provided with first to fifth conductive films formed in succession on the wiring pad. The second and fourth conductive layers are barrier metal layers, and the fourth conductive layer is a plating layer.
    [63] According to the device of the peninsula of the second aspect of the present invention, when compared with the second conductive layer having a barrier function, the third conductive layer formed on the second conductive layer formed as the barrier metal layer has a fourth conductive layer formed by the third conductive layer. It is used as a seed layer having a function of being formed into an excellent plating layer having a high adhesion to.
    [64] It is preferable that the first conductive layer serves as an adhesive layer having excellent adhesion to the underlying layer, and the fifth conductive layer serves as a wetting layer having excellent wettability to the solder ball. It is preferable that 3rd and 5th conductive layers are Cu. The barrier metal electrode preferably includes a sixth conductive layer as a protective layer to protect the edges of the first to fifth conductive layers.
    [65] Further, as a third aspect, the present invention provides a method for manufacturing an external electrode in a semiconductor device, the method comprising: forming a wiring pad on one wafer; Forming a plurality of barrier metal layers on the wiring pad; Forming a solder ball in the barrier metal layer.
    [66] In addition, as a fourth aspect, the present invention provides a method of manufacturing an external electrode in a semiconductor device, the method comprising: forming a wiring pad on one wafer; Forming a first barrier metal layer formed of nickel or a nickel alloy in a vacuum environment on the wiring pad by sputtering; Forming a second barrier metal layer formed of nickel on the seed film by plating; Forming a solder ball in the second barrier metal layer.
    [67] The third and fourth aspects of the present invention make it possible to form the semiconductor elements of the first and second aspects of the present invention.
    [68] The above or other objects, features and advantages of the present invention will be more fully understood from the following description with reference to the following drawings.
    [69] DETAILED DESCRIPTION Hereinafter, the present invention will be described in more detail with reference to the following drawings, in which like components are designated by like reference numerals.
    [70] 4, an external electrode according to the first embodiment of the present invention is formed in the insulating film 11, which covers the silicon substrate 10 with a plurality of wiring layers and an interlayer insulating film (not shown). The external electrode includes a wiring pad 12 formed of Al and formed by interposing a TiN / Ti film 13A below the insulating film 11, thereby improving adhesion between the wiring pad 12 and the insulating film 11. And improve the reliability of the wiring structure. The other insulating film 14 covering the wiring pad 12 has a two-layer structure including a silicon oxide (SiO 2) layer and a silicon oxynitride (SiON) layer, and penetrates to expose the upper portion of the wiring pad 12. Has a hole.
    [71] The upper surface of the wiring pad 12 is coated with another TiN / Ti film 13B to improve the resistance to the electro-mogration defects, thereby improving the reliability of the wiring structure. The barrier metal electrode is formed on the top surface of the through hole and the TiN / Ti film 13B around it.
    [72] Between the solder ball 20 and the wiring pad 12, the barrier metal including the solder wet Cu layer 17, the Ni-V barrier metal layer 16, the Ti adhesion film 15, and the TiN / Ti film 13B. An electrode is provided. Among them, the Ni-V barrier metal layer 16 has a very high barrier function for preventing the Sn component in the solder balls 20 from diffusing into the Al-Cu alloy in the wiring pad 12. In the assembling process, the film of the external electrode is formed by sputtering on the entire region and then patterning the through hole on the upper surface of the wiring pad 12 and the periphery of the through hole. Next, the polyimide coating (or passivation film) 18 is formed in the whole region, and the solder ball 20 is mounted on the barrier metal electrode in the through hole. The TiW adhesion film 21 is interposed between the upper outer surface of the solder-wet Cu layer 17 and the polyimide coating 18.
    [73] Referring to Fig. 5A, the Ni-V barrier metal layer 16 formed of Ni alloy has a two-layer structure including a first barrier metal layer 161 and a second barrier metal layer 162 having different crystal structures. At the bottom, the first barrier metal layer 16 is formed of a Ni-V alloy and has a granular crystal structure having tensile internal stress. At the top, the second barrier metal layer 162 is formed of a Ni-V alloy and has a columnar crystal structure having a compressive internal stress. The first and second barrier metal layers 161 and 162 are each formed by sputtering to have a thickness of about 200 nm.
    [74] In this embodiment, it is generally considered that the Ni element has a higher barrier function against Sn diffusion, and the addition of V lowers the Curie temperature of the Ni element so that Ni becomes nonmagnetic, which is suitable for sputtering of this alloy. The barrier metal film 16 is formed of a Ni-V alloy. In this example, about 7% vanadium is added to the Ni-V alloy. Elements other than vanadium which lowers the Curie temperature of Ni by adding a trace amount include tungsten (W), tantalum (Ta), silicon (Si), copper (Cu) and the like. An alloy containing nickel and one of these elements is used as the barrier metal layer.
    [75] The configuration having the tensile internal stress and the compressive internal stress of the barrier metal layer 16 can alleviate the overall internal stress of the barrier metal layer 16. This allows lower films such as the wiring pad 12 and the insulating film 14 to have low damage such as cracking of the wiring pad 12 or peel-off of the adjacent insulating film 14.
    [76] If the second barrier metal layer 162 having a columnar crystal structure alone is used for the barrier metal layer 16, the path length of the particle size diffusion becomes lower, so that the barrier function against Sn diffusion in the barrier metal layer 16 is insufficient. Done. The lower first barrier metal layer 161 has a sufficient path length along the crystal boundary, thus providing most of the barrier function for Sn diffusion.
    [77] Alternatively, the barrier metal layer 16 of FIG. 4 may have a four-layer structure as shown in FIG. 5B. The four-layer structure includes a first Ni-V barrier metal layer 161 having a granular crystal structure, a first amorphous Ni-V layer 163 having a thickness of about 10 nm, a second Ni-V barrier metal layer 162 and about 20 nm. And a second amorphous Ni-V layer 164 having a thickness of and are continuously formed on the Ti adhesion film 15. Each of the amorphous Ni-V layers 163 and 164 enhances the barrier metal function of the underlying barrier metal Ni-V layers 161 and 162 to Sn diffusion.
    [78] The four-layer structure as shown in FIG. 5B can be obtained by reducing the substrate temperature or reducing the DC sputtering voltage to an extremely low value when forming the barrier metal layer 16 by sputtering.
    [79] The amorphous film has an internal stress similar to the internal stress of a film having a granular crystal structure, and when the sputtering time is long, the surface temperature of the substrate is increased due to the collision by the plasma, and the plasma discharge is unstable at low voltage. It is difficult to obtain an amorphous film. However, experiments have demonstrated that amorphous films as thin as 10 nm have sufficient barrier function against Sn diffusion.
    [80] The two-layer barrier metal layer 16 can be obtained by controlling the RF bias voltage applied during sputtering. In Fig. 3, the relationship between the RF bias voltage during sputtering and the total amount of wafer warpage caused by the sputtered Ni-V barrier metal layer is obtained and shown by experiment. In the experiment, a Ni-V barrier metal layer is formed directly on the wafer. That is, the crystal structure of the barrier metal layer is also shown along the horizontal axis in which the RF bias voltage is plotted.
    [81] Sputtering conditions are as follows: Ar flow rate in the chamber was 20 sccm; Chamber pressure was 1.2 mTorr; DC sputtering voltage is 3.0 kW; The film thickness is 270 nm; And the RF bias wavelength is 400 kHz. Plot the wafer warpage for RF bias voltages of 0, 10, 20, 50, 100, 150, 200 and 300 watts. The barrier metal layer product is observed by electron microscopy.
    [82] As can be seen in FIG. 3, the wafer warpage for an RF bias voltage between 20 watts and 30 watts represents zero. More specifically, the internal stress in the Ni-V film sputtered at this RF bias voltage changes from tensile stress to compressive stress. In addition, in the photograph by electron microscopy, it was confirmed that at a bias voltage between 50 watts and 100 watts in which the crystal structure changes from granularity to columnar structure, a uniform bias voltage is not applied to the entire surface of the wafer. In this case, it is observed that the granular crystal structure and the columnar crystal structure are coaxially arranged in the resultant film in the outer region and the central region, respectively.
    [83] On the other hand, when the RF bias voltage is lower than the specified value, the Ni-V film result has a granular crystal structure at the DC sputtering voltage maintained at 3.0 kW, whereas when the RF bias voltage is higher than the specified value, the Ni-V film The result is a columnar crystal structure. In the manufacturing process of the semiconductor device of this embodiment, the RF bias voltage is set to 0, so that the first barrier metal layer 162 is formed to have a thickness of 200 nm, while the RF bias voltage is set to 200 watts, for example, 200 nm. A second barrier metal layer 162 having a thickness of is formed.
    [84] Referring to Fig. 6, there is shown a graph showing the relationship between the deposition rate and the DC sputtering voltage when the Ni-V alloy film is formed when the RF bias voltage is set to 0 and 200 watts. The process conditions were to set the Ar flow rate in the chamber to 60 sccm and the chamber pressure to 4 mTorr. According to FIG. 6, increasing the RF bias voltage from 6 to 200 watts reduces the deposition rate by 8-15%. By acquiring this relationship in advance, the deposition time length for obtaining a specific film thickness is determined.
    [85] FIG. 7 shows the relationship between the internal stress of the sputtered Ni-V alloy film and the RF bias voltage applied to the substrate, and the relationship between the wafer warpage and the RF bias voltage, where the process is sputtered onto a 50 nm thick Ti adhesion film. Obtain a Ni-V alloy film having a thickness of 400 nm. The chamber pressure was set at 4 mTorr and the DC sputtering voltage was set at 3 kW. In Fig. 7, the internal stress of the sputtered Ni-V alloy film changes from tensile stress to compressive stress at an RF bias voltage of about 50 watts. In addition, wafer warpage is zero at an RF bias voltage of about 50 watts. FIG. 7 shows that a Ni-V alloy film having a desired tensile internal or compressive stress can be formed by using a suitable DC sputtering voltage and adjusting the RF bias voltage.
    [86] In another experiment, a Ni-V alloy film having a thickness of 400 nm was sputtered on a wafer having a diameter of 200 mm at a DC sputtering voltage of 6 kW and a chamber pressure of 4 mTorr. In the Ni-V alloy film structure, some portions existing between the outside and the center of each wafer are observed with an electron microscope. In the entire wafer area obtained when the RF bias voltage is zero, the Ni-V alloy film has a granular crystal structure. At the position between the outer surface and the portion 75 mm away from the outer surface, the Ni-V alloy film actually has a columnar crystal structure, and has a granular crystal structure in the center region of the wafer obtained by an RF bias voltage of 50 watts. The Ni-V alloy film has a columnar crystal structure in the entire wafer area obtained by the RF bias voltage of 200 watts.
    [87] On other wafers, the RF bias voltage is set to zero in the initial stage to form a 200 nm thick Ni-V alloy layer and then raised to 200 watts to form another 200 nm thick Ni-V alloy layer. In this wafer, the Ni-V alloy film result has a two-layer structure, where the lower 200 nm thick Ni-V alloy layer has a granular crystal structure, while the upper 200 nm thick Ni-V alloy layer has a superior columnar crystal structure. Has
    [88] FIG. 8 shows the relationship between the film stress and the RF bias voltage and the relationship between the wafer warpage and the RF bias voltage, which was obtained for the case where a Ni-V alloy film having a thickness of 1000 nm was formed. The process conditions are 4mTorr chamber pressure and 9kW DC sputtering voltage. In Fig. 8, when the Ni-V alloy film has a thicker thickness, the internal stress of the Ni-V alloy film moves upward or toward the tensile stress side, so that the Ni-V alloy film has a tensile stress even at an RF voltage of 200 watts.
    [89] 9 and 10 show the relationship between the film stress and the Ar flow rate in the chamber, and the relationship between the film stress and the DC sputtering voltage, respectively. From this figure, lowering the flow rate of Ar gas, for example, lowering the sputtering pressure, provides lowering the stress on the Ni-V alloy film, such as increasing the sputtering voltage. This means that suitable sputtering conditions such as pressure, voltage, film thickness and film structure should be chosen to form a barrier metal layer that does not adversely affect the underlying wiring pad or adjacent structure. In particular, a suitable film thickness should be selected for the desired Ni-V alloy film.
    [90] FIG. 11 shows wafer warpage measured at the manufacturing stage while varying the process conditions of the sample of the external electrode. This process condition is shown in FIG. 11, where the chamber pressure, DC sputtering voltage, film thickness and bias voltage are mentioned in order for samples (1) to (5) of the single layer barrier metal layer. For each sample, mention is further made of the thickness of the upper Ni-V layer and the bias voltage for the flat two-layer barrier metal layer, such as at least three samples (6) to (8).
    [91] For example, sample (1) indicates a single layer structure, while chamber pressure is 4 mTorr, DC sputtering voltage is 3 kW, film thickness is 400 nm and RF bias voltage is 0 watt, while sample (6) indicates a two layer structure and The chamber pressure is 2 mTorr, the DC sputtering voltage is 9 kW, the film thickness of the first layer is 300 nm, the RF bias voltage for the first layer is 0 watts, the thickness of the second layer is 100 nm, and the bias voltage of the second layer is 200 watt. Illustrated.
    [92] In order to prepare such a sample, step (a), a silicon oxide film is deposited on the wafer using plasma enhanced CVD technology; Step (b), next, a Ti adhesion film and a Ni-V alloy film having a single or two-layer structure are formed; Step (c), next, a solder wet Cu layer and a TiW adhesion film are formed thereon. In each of steps (a), (b) and (c), the wafer warpage is measured as shown in FIG. Table 1 shows the measurements for each sample.
    [93]
    [94] In Table 1, the stresses MPa mentioned are positive for tensile strain and negative for compressive strain, while the stated wafer warpage is negative for tensile side and positive for compressive side. .
    [95] According to Fig. 11, when a Ni-V alloy film having a Ti adhesion film and a single layer structure is formed by sputtering, wafer warpage moves to the tensile surface due to the Ni-V alloy film having tensile internal stress. On the other hand, when a Ti adhesion film and a Ni-V alloy film having a two-layer structure are formed by sputtering, high tensile stress is relaxed. When the solder-wet Cu layer and the TiW adhesion film are formed at the same time, the wafer warpage moves toward the tensile surface. That is, before sputtering the Ni-V alloy film, the solder warping Cu layer and the TiW adhesion film may be formed by sputtering the Ni-V alloy film to move the wafer warpage to the tensile surface.
    [96] 9 and 10, an increase in the lower chamber pressure, for example the degree of vacuum, shifts the internal stress of the Ni-V alloy film to the compressive surface. This means that, while the anti-wafer effect due to wafer warpage can be minimized by controlling the internal stress of the Ni-V alloy film, the chamber pressure is controlled in consideration of the internal stress applied by other conductive films and wafer warpage. do.
    [97] In the above embodiment, the Ni-V alloy film having a single layer or two-layer structure has been upgraded. However, the Ni-V alloy film of the present embodiment may have three or more layer structures including at least one layer having tensile stress and at least one layer having compressive stress. 12 shows a table obtained by another sample of Ni-V alloy film having a total thickness of 300 nm and formed under various process conditions.
    [98] In the second column of each sample in FIG. 12, three rows represent the process conditions for the Ni-V alloy layer product formed in the Ti film. The fourth row indicates the film structure, wherein the granular crystal structure is represented by (G) while the columnar crystal structure is represented by (P). For example, the film structure of the sample 9 is a Ti film whose lower layer has a thickness of 50 nm, the first Ni-V alloy layer has a granular crystal structure, and the second Ni-V alloy layer has a thickness of 200 nm. It has a columnar crystal structure which has, and the 3rd Ni-V alloy layer has a granular crystal structure of 50 nm. In sample (9), the process conditions for the first or third Ni-V alloy layer are mentioned in the first to third horizontal lines for each sample, and the Ar flow rate, DC sputtering voltage, RF bias voltage and The film thicknesses are mentioned in order. The descriptions for the other samples 10 to 14 are similar to those in the sample 9.
    [99] From Fig. 12, the Ni-V alloy film having the three-layer structure can also improve the internal stress and mitigate wafer warpage, similarly to the two-layer structure.
    [100] In Figures 13A-13D, successive steps for manufacturing the external electrode of the first embodiment are shown. First, a multilayer wiring structure having a plurality of wiring layers and a plurality of interlayer insulating films is formed on the silicon substrate 10, and then the TiN / Ti film 13A, the wiring pad 12 and the TiN / Ti film (as part of the Al wiring) 13B) is formed in the insulating film 11. Therefore, after forming the interlayer insulating film 14 having the two-layer structure including the SiO 2 and SiON layers, as shown in FIG. 13A, the through hole is patterned so as to expose the top surface of the wiring pad 12 to be exposed. Form.
    [101] Thereafter, the Ti (or TiW) adhesion film 15, the barrier metal layer 16 formed of the Ni-V alloy including the two-layer structure, the solder wetting Cu layer and the TiW adhesion film 21 were formed on the upper portion of the interlayer insulating film 14. Deposition is carried out by sputtering inside the surface and through hole 22, thereby forming a barrier metal layer structure. Next, as shown in FIG. 13B, the barrier metal layer structure is patterned to form a barrier metal electrode having an area suitable for mounting solder balls thereon, and then a polyimide coating 18 is formed thereon. Next, as shown in FIG. 13C, the polyimide coating 18 is patterned to form an opening that exposes the top of the barrier metal electrode.
    [102] Next, the exposed surface of the top layer TiW film of the barrier metal electrode is removed by wet etching. Next, the solder ball is mounted on the barrier metal electrode to protrude from the upper portion of the through hole 19, thereby obtaining an external electrode structure as shown in FIG. 13D. The Ni-V alloy film 16 functioning as a barrier metal layer having a two-layer structure has a high barrier function corresponding to the diffusion of the Sn component in the solder ball 20. The Ni-V alloy film 20 also reduces the internal stress at the barrier metal electrode as a whole, thereby preventing the occurrence of peel-off of the wiring pad 12 or the insulating film 14 which may be caused by the internal stress. do.
    [103] Referring to FIG. 14, the external electrode according to the second embodiment of the present invention is similar to the external electrode shown in FIG. 4 except for the structure of the barrier metal electrode. More specifically, the barrier metal electrode shown in FIG. 14 includes a Ti adhesion film 31 as a first conductive film, a sputtered Ni-V barrier metal layer 32 as a second conductive film, and a seed Cu as a third conductive film. Ti disposed between the layer 33, the plated Ni barrier film 34 as the fourth conductive film, the solder wetted Cu layer 35 as the fifth conductive film, and the solder wetted Cu layer 35 and the polyimide coating 18. The adhesive film 36 is included. The Ni-V barrier metal layer 32 has a two-layer structure shown in Fig. 5A and includes a first barrier metal film having a granular crystal structure and a second barrier metal layer having a columnar crystal structure.
    [104] In the structure of the second embodiment, the seed Cu layer 33 located on top of the sputtered Ni-V barrier metal layer 32 improves the adhesion between the Ni-V barrier metal layer 32 and its upper film, The compressive force of the upper plated Ni barrier film 34 is improved. The seed Cu layer 33 is excellent in adhesiveness with the top plating Ni barrier film 34. After sputtering this Ni-V barrier film 32 in a vacuum, the sputtering of the seed Cu layer 33 in the same vacuum can prevent the appearance of a passive Ni oxide film on the Ni-V barrier metal layer 32. Since the oxide film to be formed on the seed Cu layer 33 can be easily removed, the plated Ni barrier film 34 formed thereon can improve the compressive force and the adhesion function. The plated Ni barrier film 34 has a granular crystal structure having a higher barrier function. As another method of the second embodiment, a seed Au film may be used instead of the seed Cu layer 33.
    [105] In order to manufacture the external electrode of FIG. 14, similarly to the first embodiment, the structure shown in FIG. 13A is first formed.
    [106] Following the steps of FIG. 13A, the Ti (or TiW) adhesion film 31, the Ni-V barrier metal layer 32, and the seed Cu layer 33 are formed in the insulating film 11 and the through hole 22 having a two-layer structure. Sputter on Next, the photoresist film 37 is formed thereon, and the photoresist film 37 is patterned, so that the opening part 38 which exposes the upper surface of the seed Cu layer 33 is formed. Next, after the plating Ni barrier film 34 is formed in the opening 38 by the selective plating technique, the solder wetting Cu layer 35 is formed by the selective etching technique. This structure obtained by the above-described steps is shown in FIG. The Ni-V barrier metal layer 32 has a two-layer structure as shown in Fig. 5A.
    [107] After the photoresist film 37 is removed, the TiW adhesion film 36 is sputtered on the plating Cu layer 35. Using a photoresist mask, the TiW adhesion film 36, the seed Cu layer 33, the Ni-V barrier metal layer 32, and the Ti adhesion film were continuously etched to form a polyimide coating 18 thereon. The polyimide coating 18 is for patterning the opening 39 for exposing the barrier metal electrode. The structure of FIG. 14 is removed by removing the uppermost TiW adhesion film 36 of the barrier metal electrode and the upper region of the solder wet Cu layer 35 by wet etching, and mounting the solder balls 20 in the openings 39. Acquire.
    [108] According to FIG. 16, the external electrode of the semiconductor device according to the third embodiment of the present invention is similar to the external electrode of the second embodiment except for the structure of the TiW adhesion film. More specifically, after patterning the first to fifth conductive layers 31 to 35, the TiW adhesion film 40 is formed by sputtering. The TiW adhesion film 40 is formed at the edge regions of the first to fifth conductive layers 31 to 35, the insulating layer 14 having a two-layer structure around the edge region, and the outer region at the top of the solder-wetting Cu layer 35. Cover. Similar to the second embodiment, the region of the TiW film 40 corresponding to the position of the solder ball 29 is etched away along with the corresponding region of the solder wetted Cu layer 35.
    [109] In the third embodiment, the TiW adhesion film 40 is characterized in that the Sn component in the solder ball 20 mounted on the barrier metal electrode diffuses to the barrier metal electrode through an interface between the inside of the polyimide coating 18 and the conductive layers. It acts as a protective layer to prevent it. The TiW film 40 is suitable for this purpose because of its low reactivity with solder.
    [110] Referring to FIG. 17, the external electrode of the semiconductor device according to the fourth embodiment of the present invention includes a barrier metal electrode formed after the polyimide coating 18 is formed. More specifically, the polyimide coating 18 is formed on the insulating film 14 having the teeth shown in Fig. 5A, and through holes are formed in the wiring pad 12 to expose the upper portion of the wiring pad 12. Patterned to have an opening for. Accordingly, the barrier metal electrode film structure including the Ti adhesion film 41, the Ni-V barrier metal layer 42 having the two-layer structure, and the solder wet Cu layer 43 are formed by successive sputtering. The barrier metal film structure is sputtered, the TiW adhesion film is sputtered and deposited, and then patterned. Similar to the external electrode of FIG. 16, the patterned TiW film covers the barrier metal electrode and prevents the Sn component in the solder balls 20 from diffusing to the barrier metal electrode through the interface between the conductive layers.
    [111] According to Fig. 18, the external electrode according to the first modification of the third embodiment of the present invention is manufactured as follows. First, a multilayer wiring structure including a plurality of wiring layers and a plurality of interlayer insulating films is formed on the silicon substrate 10 to form a TiN / Ti film 13A, a wiring pad 12 as part of an Al wiring, and a TiN / Ti film ( 13B) is formed in the insulating film 11. Next, an interlayer insulating film 14 having a two-layer structure including SiO 2 and SiON layers is formed, and then patterned to form a through hole exposing the upper portion of the wiring pad 12, as shown in FIG. 13A. .
    [112] Thereafter, the Ti (or TiW) adhesion film 31 and the seed Cu film 33 are successively formed on the interlayer insulating film 14 by sputtering. Next, the plated Ni barrier film 34 and the solder wetted Cu film 35 are formed by a selective etching technique. Next, after the adhesion film 31 and the seed Cu film 33 are patterned, the TiW adhesion film 40 is sputtered and patterned. Next, the polyimide coating 18 is coated and patterned to form an opening. Next, the exposed surface of the top TiW film of the barrier metal electrode is removed by a wet etching method. Next, solder balls are mounted on the barrier metal.
    [113] According to FIG. 19, the external electrode according to the second modification of the third embodiment of the present invention is similar to the external electrode shown in FIG. 18 except for the patterning process of the barrier metal electrode. An optional plating technique is used to form the plated Ni barrier film 34 and the solder wetted Cu film 35, and the TiW adhesion film 40 is formed by sputtering. Next, the TiW adhesion film 40, the seed Cu film 33, and Ti (or TiW) adhesion film 31 are patterned. Next, the polyimide coating 18 is coated and patterned to form an opening. Next, wet etching removes the exposed surface of the top TiW film of the barrier metal electrode. Next, solder balls are mounted on the barrier metal.
    [114] According to FIG. 20, the external electrode according to the third modification of the third embodiment of the present invention is similar to the external electrode shown in FIG. 19 except for the patterning process of the polyimide film. After coating and patterning the polyimide coating 18 to form an opening, a barrier metal electrode, a seed Cu film 33, a plated Ni barrier film 34, and a solder including a Ti (or TiW) adhesion film 31 are formed. A barrier metal electrode comprising a wet Cu film 35 is formed. Next, solder balls are mounted on the barrier metal.
    [115] The foregoing embodiments have been described for the purpose of illustration only, and are not intended to limit the invention to the embodiments described above, and are normally defined in the art within the scope of the invention, without departing from the spirit and scope of the claims. It should be understood that various modifications and changes can be easily made by those skilled in the art.
    [116] As described above, according to the present invention, according to the semiconductor device of the present invention and the semiconductor device manufactured by the method of the present invention, the barrier metal electrode structure and the barrier metal electrode structure have a sufficient barrier function against Sn diffusion of the solder ball. Since it is possible to form a barrier metal layer that does not exert a high stress on the surrounding structure, the present invention has a remarkable effect of providing a semiconductor device having an external electrode structure with increased reliability.
    权利要求:
    Claims (27)
    [1" claim-type="Currently amended] An external electrode including a wiring pad 12, a barrier metal electrode, and a solder ball 20 continuously formed on the wafer,
    The barrier metal electrode is characterized in that it comprises a plurality of barrier metal layers (16) having a common element and having different internal stresses and / or different crystal structures.
    [2" claim-type="Currently amended] The semiconductor device according to claim 1, wherein said barrier metal layer (16) comprises nickel or a nickel alloy.
    [3" claim-type="Currently amended] 3. The semiconductor device of claim 2, wherein the nickel alloy is selected from the group consisting of nickel vanadium, nickel tungsten, nickel tantalum, nickel silicon, and nickel copper alloys.
    [4" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the barrier metal layer (16) has a first barrier metal layer (161) having a tensile internal stress and a second barrier metal layer (162) having a compressive internal stress.
    [5" claim-type="Currently amended] The semiconductor device according to claim 1, wherein the barrier metal layer (16) comprises a first barrier metal layer (16) having a granular crystal structure and a second barrier metal layer (162) having a columnar crystal structure.
    [6" claim-type="Currently amended] 6. The barrier metal layer 16 further comprises first and second amorphous layers 163, 164 formed on the first and second barrier metal layers 161, 162, respectively, of nickel or nickel alloy. A semiconductor device comprising a.
    [7" claim-type="Currently amended] A semiconductor device according to claim 1, wherein the barrier metal electrode comprises a protective layer (40, 44) for applying edges of the barrier metal layer (32, 34, 42).
    [8" claim-type="Currently amended] An external electrode including a wiring pad 12 formed on the wafer, a barrier metal electrode, and a solder ball 20,
    The barrier metal electrode has first to fifth conductive films 31 to 35 formed continuously on the wiring pad 12,
    The second and fourth conductive films (32, 24) are barrier metal layers, and the fourth conductive film (34) is a plated film.
    [9" claim-type="Currently amended] 9. The semiconductor device according to claim 8, wherein said second conductive film (32) comprises a first conductive layer (161) having a granular crystal structure and a second conductive layer (162) having a columnar crystal structure.
    [10" claim-type="Currently amended] 10. A semiconductor device according to claim 9, wherein the second conductive film (32) comprises a first conductive layer (161) having a tensile internal stress and a second conductive layer (162) having a compressive internal stress.
    [11" claim-type="Currently amended] 9. A semiconductor device according to claim 8, wherein said third conductive layer (33) comprises copper and said second and fourth conductive films (32, 34) comprise nickel as a main component.
    [12" claim-type="Currently amended] 9. A semiconductor device according to claim 8, wherein the thickness of the fourth conductive film (34) is thicker than the thickness of the second conductive film (32).
    [13" claim-type="Currently amended] 9. The semiconductor device according to claim 8, wherein said barrier metal electrode further comprises a protective film (40) covering corner regions of said first to fourth conductive films (31 to 35).
    [14" claim-type="Currently amended] Forming a wiring pad 12 on the wafer;
    Forming a plurality of barrier metal layers (16) on the wiring pads (12); And
    Forming a solder ball (20) on the barrier metal layer (16).
    [15" claim-type="Currently amended] The method of manufacturing an external electrode of a semiconductor device according to claim 14, wherein said plurality of barrier metal layers (161, 162) comprise nickel or a nickel alloy and have different internal stresses.
    [16" claim-type="Currently amended] The method of manufacturing an external electrode of a semiconductor device according to claim 14, wherein said plurality of barrier metal layers (161, 162) comprise nickel or a nickel alloy and have different crystal structures.
    [17" claim-type="Currently amended] 15. A method according to claim 14, wherein the plurality of barrier metal layers (16) comprise amorphous layers (163, 164) formed of nickel or nickel alloys.
    [18" claim-type="Currently amended] 15. The method of claim 14, wherein the nickel alloy is selected from the group consisting of nickel vanadium nickel tungsten, nickel tantalum, nickel silicon, and nickel copper.
    [19" claim-type="Currently amended] The method of claim 14, wherein the forming of the barrier metal layer comprises controlling an internal stress or a crystal structure of the barrier metal layer by controlling a bias voltage applied to the wafer. .
    [20" claim-type="Currently amended] Forming a wiring pad 12 on the wafer;
    Forming a first barrier metal layer (32) made of nickel or a nickel alloy by sputtering in vacuum on the wiring pad (12);
    Forming a seed film (33) on the first barrier metal film (32) in the vacuum;
    Forming a second barrier metal layer (34) made of nickel on said seed film by plating; And
    Forming the solder ball (20) on the second barrier metal layer (34).
    [21" claim-type="Currently amended] 21. The method of claim 20, wherein the nickel alloy is selected from the group consisting of nickel vanadium, nickel tungsten, nickel tantalum, nickel silicon, and nickel copper alloys.
    [22" claim-type="Currently amended] 21. The semiconductor according to claim 20, wherein forming the first barrier metal layer comprises controlling an internal stress or crystal structure of the first barrier metal layer 32 by controlling a bias voltage applied to the wafer. Method for manufacturing an external electrode of the device.
    [23" claim-type="Currently amended] An external electrode comprising a wiring pad 12, a barrier metal electrode, and a solder ball 23 continuously formed on the wafer,
    The barrier metal electrode includes first to fourth conductive films 31, 33, 34, 35 formed continuously on the wiring pad 12,
    And the third conductive film (34) is a barrier metal film and a plated film.
    [24" claim-type="Currently amended] 24. A semiconductor device according to claim 23, wherein the second and fourth conductive films (33, 35) comprise copper, and the third conductive layer contains nickel as its main component.
    [25" claim-type="Currently amended] 24. A semiconductor device according to claim 23, wherein the thickness of the fourth conductive film (35) is thicker than the thickness of the second conductive film (33).
    [26" claim-type="Currently amended] The semiconductor device of claim 23, wherein the barrier metal electrode comprises a protective layer covering an edge of the barrier metal layer.
    [27" claim-type="Currently amended] 27. The semiconductor device according to claim 26, wherein the protective layer (40) comprises two layers of conductive film or conductive film and insulating film.
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    同族专利:
    公开号 | 公开日
    JP2003031576A|2003-01-31|
    US20030025202A1|2003-02-06|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-07-17|Priority to JPJP-P-2001-00216246
    2001-07-17|Priority to JP2001216246A
    2002-07-18|Application filed by 닛뽕덴끼 가부시끼가이샤
    2003-01-23|Publication of KR20030007227A
    优先权:
    申请号 | 申请日 | 专利标题
    JPJP-P-2001-00216246|2001-07-17|
    JP2001216246A|JP2003031576A|2001-07-17|2001-07-17|Semiconductor element and manufacturing method therefor|
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